1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a multilevel interconnection structure and, more particularly, a method of burying a conductive metal in a via hole formed in an insulating interlayer to connect wiring lines between layers.
2. Related Background Art
With the recent advance of micropatterning of a semiconductor device, a technology for burying a conductive metal in a via hole (formed in an insulating interlayer) serving as a connecting portion between lower and upper wiring layers is important when a multilevel interconnection structure is formed in the semiconductor device.
For example, as a method of forming a low-resistance buried plug (via plug) in a fine via hole having a diameter of 1.0 .mu.m or less, the selective Al-CVD (aluminum chemical vapor deposition) method using an organic Al compound as a material is proposed. A method using the selective Al-CVD method is disclosed in U.S. Pat. No. 5,151,305, in which DMAH (dimethylaluminumhydride) and hydrogen are used as materials and Al is deposited not on the surface of an insulating layer but on a semiconductor or conductive material. According to this method, Al is deposited in a via hole formed in the insulating layer, and subsequently, Al is deposited on the entire surface by sputtering method.
However, when the lower wiring layer consists of Al or an Al alloy, it is difficult to ideally perform the selective Al-CVD method. On the other hand, some processes are disclosed in, e.g., Japanese Patent Laid-Open No. 2-132825, which are required to satisfactorily form a via plug by the selective W-CVD method using a WF.sub.6 gas as a material even when the lower wiring layer consists of Al or an Al alloy.
In practice, an aluminum oxide (alumina) film is formed on the Al surface exposed to the bottom of the via hole to interfere with formation of a via plug by the selective W-CVD method. For this reason, this example cited discloses that the alumina film must be removed by an Ar plasma process, and that the surface of the insulating interlayer must be activated by the Ar plasma to degrade selectivity. More specifically, the Ar plasma process (removal of the alumina layer activation of the surface of the insulating interlayer) and a halogen plasma process (stabilization of the surface of the insulating interlayer) must be sequentially performed, or two processes must be simultaneously performed in a plasma atmosphere containing a gas mixture of Ar and halogen.